With increasing demands for advanced device structures, the use of dopants to control the conducting channel in traditional CMOS devices is reaching its limits. As CMOS devices are scaled to the nanometer regime, SOI structures including fully depleted (FD) and partially depleted (PD) structures have provided an evolutionary pathway for MOSFETS operating at low power. CMOS designs below about 0.1 microns are plagued by shortcomings such as short channel effects (SCE) and gate oxide tunneling. In addition, sever restraints are placed on the uniformity of the active silicon channel region which is correspondingly reduced in dimension. One approach to overcome such shortcomings is to change the device structure such that the gate length may be scaled down while using thicker gate oxides and increased active silicon channel dimensions.
For example FET designs have included forming non-planar active silicon regions by forming fin-like silicon channel structures also referred to as finFETs and triple gated structures referred to a tri-gate FETs.
While these structures have been shown to have acceptable short channel behavior and may be formed with conventional gate oxide thicknesses to overcome gate oxide tunneling, majority carrier mobility is frequently compromised by prior art formation processes.
There is therefore a continuing need in the integrated circuit (IC) semiconductor device processing art to develop advanced CMOS FET devices including multiple gate regions.
It is therefore an object of the invention to provide an advanced CMOS FET device structure including multiple gate regions.